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1 for more information www.linear.com/lt6020 20 v output step response typical a pplica t ion fea t ures descrip t ion dual micropower, 5v/s precision rail-to-rail output amplifier the lt ? 6020 is a low power, enhanced slew rate, precision operational amplifier. the proprietary circuit topology of this amplifier gives excellent slew rate at low quiescent power dissipation without compromising precision or settling time. in addition, unique input stage circuitry allows the input impedance to remain high during input voltage steps as large as 5 v. the combination of preci - sion specs along with fast settling makes this part ideal for mux applications. the low quiescent current of the lt6020 along with its ability to operate on supplies as low as 3 v make it useful in portable systems. the lt6020-1 features a shutdown mode which reduces the typical supply current to 1.4a. the lt6020 is available in the small 8- lead dfn and 8-lead msop packages. the lt6020-1 is available in a 10-lead dfn package. 16- bit dac with 10 v output swing a pplica t ions n precision signal processing n 18-bit dac amplifier n multiplexed adc applications n low power portable systems n low power wireless sensor networks l, lt , lt c , lt m , linear technology, smartmesh and the linear logo are registered trademarks and softspan is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. patent pending. n excellent slew rate to power ratio n slew rate: 5v/s n maximum supply current: 100a/amplifier n maximum offset voltage: 30v n maximum offset voltage drift: 0.5v/c n high dynamic input impedance n fast recovery from shutdown n maximum input bias current: 3na n no output phase inversion n gain bandwidth product: 400khz n wide specified supply range: 3v to 30v n operating temperature range: C40c to 125c n dfn and ms8 packages n rail-to-rail outputs 60201 ta01a v out gnd ref v dd ltc2642 1f r fb inv 16-bit dac control logic ? + cs din clr sclk 16-bit data latch 16-bit shift register 0.1f 3.8v dc to 5.5v dc 0.1f 15v ?15v LT5400-1 10k matched resistor network ? + 1/2 lt6020 1/2 lt6020 10pf v out power-on reset lt1019-2.5 in out gnd 60201 ta01b 5v/div 5v/div 20s/div cs v out lt 6020 / lt 6020 -1 60201fa
2 for more information www.linear.com/lt6020 p in c on f igura t ion a bsolu t e maxi m u m r a t ings total supply voltage (v + to v C ) ................................. 36 v di fferential input voltage ( within supplies ) ............... 36 v in put voltage ( dgnd , en ) ( relative to v C ) ................ 36 v inp ut current (+ in , C in , dgnd , en ) ..................... 1 0 ma output short - circuit duration .......................... in definite ( note 1) top view dd package 8-lead (3mm 3mm) plastic dfn 5 6 7 8 4 3 2 1out a ?in a +in a v ? v + out b ?in b +in b 9 a b ja = 43c/w, jc = 5.5c/w exposed pad ( pin 9) is connected to v C (pin 4) (pcb connection optional) top view 11 dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 v + out b ?in b +in b en out a ?in a +in a v ? dgnd a b ja = 43c/w, jc = 5.5c/w exposed pad ( pin 11) is connected to v C (pin 4) (pcb connection optional) 1 2 3 4 outa ?ina +ina v ? 8 7 6 5 v + outb ?inb +inb top view ms8 package 8-lead plastic msop a b ja = 163c/w, jc = 40c/w o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range lt6020idd#pbf lt6020idd#trpbf lgmc 8-lead (3mm 3mm) plastic dfn C40c to 85c lt6020hdd#pbf lt6020hdd#trpbf lgmc 8-lead (3mm 3mm) plastic dfn C40c to 125c lt6020idd-1#pbf lt6020idd-1#trpbf lgkf 10-lead (3mm 3mm) plastic dfn C40c to 85c lt6020hdd-1#pbf lt6020hdd-1#trpbf lgkf 10-lead (3mm 3mm) plastic dfn C40c to 125c lt6020ims8#pbf lt6020ims8#trpbf ltgjg 8-lead plastic msop C40c to 85c lt6020hms8#pbf lt6020hms8#trpbf ltgjg 8-lead plastic msop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ operating and specified temperature range i- gr ade ................................................. C40 c to 85 c h- gr ade ............................................ .C 40 c to 125 c junction temperature ........................................... 15 0 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) ................... 30 0 c lt 6020 / lt 6020 -1 60201fa
3 for more information www.linear.com/lt6020 e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v os input offset voltage dd packages t a = C40 to 85c t a = C40 to 125c l l 20 70 110 120 v v v ms8 package t a = C40 to 85c t a = C40 to 125c l l 5 30 70 80 v v v ?v osi ?temp input offset v oltage drift (note 2) dd packages l C0.8 0.3 0.8 v/c ms8 package l C0.5 0.2 0.5 v/c ?v osi ?time long t erm input offset voltage stability l 0.2 v/mo i b input bias current t a = C40 to 85c t a = C40 to 125c l l C3 C3 C10 0.1 3 3 10 na na na i os input offset current t a = C40 to 85c t a = C40 to 125c l l C1 C1 C2 0.1 1 1 2 na na na input noise v oltage 0.1hz to 10hz 1.1 v p-p e n input noise voltage density f = 10hz f = 1khz 50 46 nv / hz nv/hz in input noise current density f = 1khz 37 fa/ hz c in input capacitance common mode differential mode 1.5 2.5 pf pf r in input resistance common mode differential mode 17 20 g m v icm common mode input range l v C + 1.2 v + C 1.4 v cmrr common mode rejection ratio v cm = C13.8v to 13.6v l 120 120 132 db db psrr supply rejection ratio v s = 3v to 30v l 120 118 140 db db a vol large-signal voltage gain r l = 6.98k, v out = 14v l 110 108 116 db db r l = 100k, v out = 14.5v l 126 126 138 db db v ol output swing low (v out C v C ) r l = 10k t a = C40 to 85c t a = C40 to 125c l l 130 200 250 300 mv mv mv v oh output swing high (v + C v out ) r l = 10k t a = C40 to 85c t a = C40 to 125c l l 100 140 165 190 mv mv mv i sc short-circuit current v out = 0v, sourcing t a = C40 to 85c t a = C40 to 125c l l 5.5 5 8 ma ma ma v out = 0v, sinking t a = C40 to 85c t a = C40 to 125c l l 5.5 5.5 11 ma ma ma the l denotes the specifications which apply over the specified temperature range , otherwise specifications are at t a = 25c, v s = 15 v, v cm = v out = mid - supply , v dgnd = 0v, v en = 5v. dgnd and en specifications only apply to the lt 6020 -1. lt 6020 / lt 6020 -1 60201fa
4 for more information www.linear.com/lt6020 e lec t rical c harac t eris t ics symbol parameter conditions min typ max units sr slew rate a vcl = 1, 10v step t a = C40 to 85c t a = C40 to 125c l l 3 2.4 2.4 5 v /s v/s v/s a vcl = 1, 5v step t a = C40 to 85c t a = C40 to 125c l l 1.4 1.1 1 2.4 v /s v/s v/s gbw gain-bandwidth product f o = 10khz l 290 400 khz minimum supply voltage guaranteed by psrr l 3 v i s supply current per amplifier t a = C40 to 85c t a = C40 to 125c l l 90 100 125 140 a a a supply current in shutdown v en = 0.8v t a = C40 to 85c t a = C40 to 125c l l 1.4 3 3.2 3.6 a a a t s settling time (a v = 1) 0.1% 5v output step 0.01% 5v output step 0.0015% 5v output step 0.0015% 10v output step 6 7.8 13.8 12.4 s s s s t on enable time a v = 1 100 s v dgnd dgnd pin voltage range l v C v + C 3 v i dgnd dgnd pin current l C200 C400 na i en en pin current l C100 C200 na v enl en pin input low voltage relative to dgnd l 0.8 v v enh en pin input high voltage relative to dgnd l 1.7 v the l denotes the specifications which apply over the specified temperature range , otherwise specifications are at t a = 25c, v s = 15 v, v cm = v out = mid - supply , v dgnd = 0v, v en = 5v. dgnd and en specifications only apply to the lt 6020 -1. lt 6020 / lt 6020 -1 60201fa
5 for more information www.linear.com/lt6020 e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v os input offset voltage dd packages t a = C40 to 85c t a = C40 to 125c l l 20 100 140 150 v v v ms8 package t a = C40 to 85c t a = C40 to 125c l l 5 45 85 95 v v v ?v osi ?temp input offset v oltage drift (note 2) dd packages l C0.8 0.3 0.8 v/c ms8 package l C0.5 0.2 0.5 v/c ?v osi ?time long t erm input offset voltage stability l 0.2 v/mo i b input bias current 1 na i os input offset current 0.1 na input noise voltage 0.1hz to 10hz 1.1 v p-p e n input noise voltage density f = 10hz f = 1khz 50 46 nv / hz nv/hz in input noise current density f = 1khz 37 fa/ hz c in input capacitance common mode differential mode 1.5 2.5 pf pf r in input resistance common mode differential mode 17 20 g m v icm common mode input range l v C + 1.2 v + C 1.4 v cmrr common mode rejection ratio v cm = 1.2v to 1.6v 125 db psrr supply rejection ratio v s = 3v to 30v l 120 118 140 db db a vol large-signal voltage gain r l = 6.98k, v out = 0.5v to 2.5v l 98 98 108 db db r l = 100k, v out = 0.5v to 2.5v 136 db v ol output swing low (v out C v C ) r l = 10k t a = C40 to 85c t a = C40 to 125c l l 45 100 130 150 mv mv mv v oh output swing high (v + C v out ) r l = 10k t a = C40 to 85c t a = C40 to 125c l l 55 80 90 100 mv mv mv i sc short-circuit current v out = 1.5v, sourcing t a = C40 to 85c t a = C40 to 125c l l 3.5 3.5 6 ma ma ma v out = 1.5v, sinking t a = C40 to 85c t a = C40 to 125c l l 5.5 5.5 8 ma ma ma sr slew rate (note 3) a vcl = C1, 2v step 0.2 v/s gbw gain-bandwidth product f o = 10khz 400 khz minimum supply voltage guaranteed by psrr l 3 v the l denotes the specifications which apply over the specified temperature range , otherwise specifications are at t a = 25c, v s = 3v, v cm = v out = mid - supply , v dgnd = 0v, v en = 3v. dgnd and en pin specifications only apply to the lt 6020 -1. lt 6020 / lt 6020 -1 60201fa
6 for more information www.linear.com/lt6020 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: guaranteed by design. note 3: the slew rate of the lt6020 increases with the size of the input step. at lower supplies, the input step size is limited by the input common mode range. this trend can be seen in the typical performance characteristics. e lec t rical c harac t eris t ics symbol parameter conditions min typ max units i s supply current per amplifier t a = C40 to 85c t a = C40 to 125c l l 85 95 120 135 a a a supply current in shutdown v en = 0.8v t a = C40 to 85c t a = C40 to 125c l l 0.9 1.1 1.5 3 a a a t s settling time (a v = C1) 0.1% 2.4v output step 0.01% 2.4v output step 0.0015% 2.4v output step 12.4 21.2 39.2 s s s t on enable time a v = 1 120 s v dgnd dgnd pin voltage range l v C v + C 3 v i dgnd dgnd pin current C200 na i en en pin current C100 na v enl en pin input low voltage relative to dgnd l 0.8 v v enh en pin input high voltage relative to dgnd l 1.7 v the l denotes the specifications which apply over the specified temperature range , otherwise specifications are at t a = 25c, v s = 3v, v cm = v out = mid - supply , v dgnd = 0v, v en = 3v. dgnd and en pin specifications only apply to the lt 6020 -1. lt 6020 / lt 6020 -1 60201fa
7 for more information www.linear.com/lt6020 typical p er f or m ance c harac t eris t ics typical distribution of input offset voltage voltage offset shift vs lead free ir reflow offset voltage vs supply voltage typical distribution of input offset voltage drift offset voltage vs input common mode voltage typical distribution of input offset voltage typical distribution of input offset voltage warm - up drift t a = 25c, v s = 15 v, r l = 100 k, unless otherwise specified . input offset voltage ( v ) ?30 number of units 1400 1200 1000 800 600 400 200 0 20 60201 g31 30 ?10?20 100 2932 parts ms8 package input offset voltage ( v ) ?70 ?50 ?30 number of units 4000 1500 1000 2500 2000 3500 3000 500 0 60201 g32 70 30 50 ?10 100 14930 parts dd8 and dd10 packages input offset voltage drift (v/c) ?0.80 number of channels 40 15 10 25 20 35 30 5 0 60201 g33 0.40 0 0.20 ?0.60 ?0.20 ?0.40 144 units dd8 and dd10 packages input offset voltage drift (v/c) ?0.50 number of channels 100 40 50 60 70 80 90 10 20 30 0 60201 g34 0.10 ?0.10 0 ?0.40 ?0.20 ?0.30 350 units ms8 package time (ms) 1 change in input offset voltage (v) 5 3 4 0 ?2 ?3 2 1 ?1 ?4 ?5 6 3 5 60201 g01 7 2 4 input voltage offset shift (v) ?2 number of channels 14 2 4 6 8 10 12 0 60201 g35 12 8 10 0 2 64 40 parts ms8 package total supply voltage (v) 0 offset voltage (v) 30 10 20 0 10 ?20 ?30 16 32 8 24 60201 g02 36 12 28 4 20 input common mode voltage (v) ?15 offset voltage (v) 40 20 30 10 0 ?10 ?20 ?30 ?40 10 ?10 5 60201 g03 15 ?5 0 lt 6020 / lt 6020 -1 60201fa
8 for more information www.linear.com/lt6020 typical p er f or m ance c harac t eris t ics large -signal transient response (10 v step ) slew rate vs temperature (5 v step ) slew rate vs temperature (10 v step ) t a = 25c, v s = 15 v, r l = 100 k, unless otherwise specified . 10s/div a v = 1 2v/div 60201 g10 temperature (c) ?50 slew rate (v/s) 5 4 3 2 1 0 75 100 ?25 50 60201 g11 125 0 25 rising edge falling edge temperature (c) ?50 slew rate (v/s) 7 6 5 4 3 2 1 0 75 100 ?25 50 60201 g12 125 0 25 rising edge falling edge input bias current vs temperature input bias current vs differential input voltage 0.1 hz to 10 hz voltage noise voltage noise density vs frequency temperature (c) ?50 input bias current (na) 4 3 2 1 0 ?1 100 ?25 75 60201 g04 125 250 50 differential input voltage (v) ?6 input bias current (a) 1.00 0.75 0.50 0.25 ?0.25 ?0.50 ?0.75 0 ?1.00 5 ?5 4 60201 g05 6 ?1?2?4 ?3 3210 ib+ ib? 500nv/div 60201 g06 1s/div frequency (hz) voltage noise density (nv/ hz) 60201 g07 1000 100 10 0.01 0.1 1 1k 10k 10010 frequency (khz) maximum undistorted output voltage (v p-p ) 60201 g08 35 30 25 20 15 0 5 10 0.1 1 10 thd < 40dbc 10s/div 1v/div 60201 g09 a v = 1 large -signal transient response (5 v step ) maximum undistorted output amplitude vs frequency lt 6020 / lt 6020 -1 60201fa
9 for more information www.linear.com/lt6020 slew rate vs input step small -signal transient response overshoot vs capacitive load typical p er f or m ance c harac t eris t ics psrr vs frequency cmrr vs frequency open - loop gain and phase vs frequency gain vs frequency open loop gain vs load output impedance vs frequency t a = 25c, v s = 15 v, r l = 100 k unless otherwise specified . 2s/div 5mv/div 60201 g14 a v = 1 300pf 0pf 100pf capacitive load (pf) 0 overshoot (%) 50 45 40 35 30 25 20 15 10 5 0 400 500 600 700 800 900 100 60201 g15 1000 200 300 v s = 1.5v v s = 15v a v = 1 frequency (hz) power supply rejection ratio (db) 60201 g16 160 140 120 100 80 60 0 20 40 0.01 0.1 1m 1 10 100 1k 10k 100k ?psrr +psrr frequency (hz) common mode rejection ratio (db) 60201 g17 140 120 100 80 60 0 20 40 0.1 1m 1 10 100 1k 10k 100k frequency (hz) open loop gain (db) open loop phase (degrees) 60201 g18 140 ?45 ?90 ?135 ?180 ?225 120 100 80 60 ?20 0 20 40 10m1m 1 10 100 1k 10k 100k v s = 30v v s = 3v frequency (hz) gain (db) 60201 g19 3 0 ?3 ?6 ?9 ?12 10k 100k 1m c l = 330pf a v = 1 c l = 100pf a v = 1 c l = 100pf a v = ?1 load current (ma) open loop gain (db) 60201 g20 150 140 130 120 110 100 90 60 70 80 0.1 1 10 v out = 14.5v frequency (hz) output impedance () 60201 g21 1000 100 10 1 0.1 0.01 100 1000 1m 10m 100k 10k input step size (v p-p ) 0 slew rate (v/s) 8 7 6 5 4 3 2 1 0 20 25 5 60201 g13 30 10 15 a v = 1 rising edge falling edge lt 6020 / lt 6020 -1 60201fa
10 for more information www.linear.com/lt6020 typical p er f or m ance c harac t eris t ics negative output overdrive recovery positive output overdrive recovery crosstalk vs frequency t a = 25c, v s = 15 v, r l = 100 k unless otherwise specified . 60201 g29 100s/div 0v input 200mv/div a v = ?100 output 5v/div 60201 g30 100s/div 0v input 200mv/div a v = ?100 output 5v/div frequency (hz) crosstalk (db) 60201 g28 ?40 ?60 ?80 ?100 ?120 ?140 100 1k 1m 100k 10k v dgnd = 0v v en = 5v supply current vs supply voltage shutdown supply current vs temperature start - up response enable / disable response output saturation voltage vs sink current ( output low ) output saturation voltage vs source current ( output high ) total supply voltage (v) 0 supply current/amplifier (a) 160 140 120 100 80 60 40 20 0 25 30 5 20 60201 g22 10 15 125c 85c 25c ?40c temperature (c) ?50 shutdown supply current (a) 3.0 2.5 2.0 1.5 1.0 0.5 0 75 100 125 ?25 50 60201 g23 0 25 v s = 30v v s = 3v v en 5v/div v out 5v/div 0v 0v 60201 g24 100s/div a v = 1 v in = 5v p-p at 50khz load current (ma) output low saturation voltage (v) 60201 g26 1 0.1 0.01 0.1 1 10 t a = 125c t a = 85c t a = ?40c t a = 25c load current (ma) output high saturation voltage (v) 60201 g27 1 0.1 0.01 0.1 1 10 t a = 125c t a = 85c t a = ?40c t a = 25c v en 5v/div 0v i(v + ) 200a/div 0a 60201 g24 20s/div lt 6020 / lt 6020 -1 60201fa
11 for more information www.linear.com/lt6020 p in func t ions out: amplifier output. Cin: inverting input of the amplifier. +in: noninverting input of the amplifier. v C : negative power supply. a bypass capacitor should be used between supply pins and ground. additional bypass capacitance may be used between the power supply pins. dgnd ( lt6020-1 only): reference for en pin. it is normally tied to ground. dgnd must be in the range from v C to v + C3v. if grounded, v + must be 3 v. the en pin threshold is specified with respect to the dgnd pin. dgnd cannot be floated. en ( lt6020-1 only): enable input. this pin must be connected high, normally to v + , for the amplifiers to be functional. en is active high with the threshold approxi- mately two diodes above dgnd. en cannot be floated. the shutdown threshold voltage is specified with respect to the voltage on the dgnd pin. v + : positive power supply. a bypass capacitor should be used between supply pins and ground. additional bypass capacitance may be used between the power supply pins. s i m pli f ie d s che m a t ic 60201 bd +in v + ?in 5k 5k out en 200k 200k lt6020-1 only dgnd v ? load class ab drive a pplica t ions i n f or m a t ion preserving low power operation the proprietary circuitry used in the lt6020 provides an excellent combination of low power, low offset and en - hanced slew rate. normally an amplifier with higher supply current would be required to achieve this combination of slew rate and precision. special care must be taken to ensure that the low power operation is preserved. the choice of feedback resistor values impacts several op-amp parameters as noted in the feedback compo - nents section . it should also be noted that the output of the amplifier must drive this network. for example, in a gain of two with a total feedback resistance of 10 k and an output voltage of 14 v, the amplifiers output will need to supply 1.4 ma of current. this current will ultimately come from a supply. lt 6020 / lt 6020 -1 60201fa
12 for more information www.linear.com/lt6020 a pplica t ions i n f or m a t ion figure 1. settling time is essentially flat smaller inputs the lt6020 slew rate approaches the slew rate more common in traditional micropower amplifiers. input bias current the design of the input stage of the lt6020 is more so - phisticated than that shown in the simplified schematic. it uses both npn and pnp input differential amplifiers to sense the input differential voltage. as a result the speci - fied input bias current can flow in or out of the input pins. multiplexer applications/high dynamic input impedance the lt6020 has features which make it desirable for multiplexer applications, such as the application featured on the back page of this data sheet. when the channels of the multiplexer are cycled, the output of the multiplexer can produce large voltage transitions. normally, bipolar amplifiers have back-to-back diodes between the inputs, which will turn on when the input transient voltage exceeds 0.7v, causing a large transient current to be conducted from the amplifier output stage back into the input driving circuitry. the driving circuitry then needs to absorb this current and settle before the amplifier can settle. the lt6020 uses 5.5 v zener diodes to protect its inputs which dramatically increases its input i mpedance with input steps as large as 5v. achieving rail-to-rail operation without rail-to-rail inputs the lt6020 output is able to swing close to each power supply rail, but the input stage is limited to operating between v C + 1.2 v and v + C 1.4 v. for many inverting applications and noninverting gain applications, this is largely inconsequential. figure 2 shows the basic op amp configurations, what happens to the op amp inputs and whether or not the op amp must have rail-to-rail inputs. the circuit of figure 3 shows an extreme example of the inverting case. the input voltage at the 100 k resistor can swing 13.5 v and the lt6020 will output an inverted, output step (v p-p ) 5 settling time (s) 30 25 20 15 10 5 0 20 60201 f01 25 10 15 0.0015% a v = 1 0.01% the supply current of the lt6020 increases with large differential input voltages. normally, this does not impact the low power nature of the lt6020 because the ampli - fier is forcing the two inputs to be at the same potential. conditions which cause differential input voltage to appear should be avoided in order to preserve the low power dis - sipation of the lt6020. this includes but is not limited to: operation as a comparator, excessive loading on the output and overdriving the input. enhanced slew rate the lt6020 uses a proprietary input stage which provides an enhanced slew rate without sacrificing input precision specs such as input offset voltage, common mode rejection and noise. the unique input stage of the lt6020 allows the output to quickly slew to its final value when large signal input steps are applied. this enhanced slew characteristic allows the lt6020 to quickly settle the output to 0.0015% independent of input step size as shown in figure 1. typi - cal micropower amplifiers cannot process large amplitude signals with this speed. as shown in the typical perfor- mance cur ves, when the lt6020 is configured in unity gain and a 10 v step is applied to the input the output will slew at 5 v/s. in this same configuration, a 5 v input step will slew the output at 2.4 v/s. furthermore, a 0.7 v input step will lower the slew rate to 0.2 v/s. note that for these lt 6020 / lt 6020 -1 60201fa
13 for more information www.linear.com/lt6020 a pplica t ions i n f or m a t ion figure 2. some op amp configurations do not require rail - to - rail inputs to achieve rail - to - rail outputs r g v ref noninverting: a v = 1 + r f /r g inputs move by as much as v in , but the output moves more input may not have to be rail-to-rail noninverting: a v = 1 inputs move by as much as output input must be rail-to-rail for overall circuit rail-to-rail performance inverting: a v = ?r f /r g op amp inputs do not move, but are fixed at dc bias point v ref input does not have to be rail-to-rail v in r f ? + v in v ref r f r g ? + v in 60201 f02 ? + the specified input voltage range as shown in figure 4. however the open loop gain is significantly reduced. while the output roughly tracks the input, the reduction in open loop gain degrades the accuracy of the lt6020 in this region. exceeding the input common mode range also causes a significant increase in input bias current as shown in figure 5. the output of the lt6020 is guaranteed over the specified temperature range not to phase invert as long as the input voltage does not exceed the supply voltage. preserving input precision preserving the input accuracy of the lt6020 requires that the application circuit and pc board layout do not figure 4. no phase inversion 0v5v/div ?20v ?10v 20v 10v 200s/div 60201 f04 output input ?v cm limit +v cm limit v s =15v a v = 1 figure 3. extreme inverting case : circuit operates properly with input voltage swing well outside op amp supply rails 1.5v ?1.5v 10k, 0.1% 100k, 0.1% v in 1.35v output swing 13.5v swings well outside supply rails ? + lt6020 1880 f03 divided-by-ten version of the input voltage. the output accuracy is limited by the resistors to 0.2%. output referred, this error becomes 2.7 mv. the 30 v input offset voltage contribution, plus the additional error due to input bias current times the ~10 k effective source impedance, contribute only negligibly to error. phase inversion the lt6020 input stage is limited to operating between v C + 1.2 v and v + C 1.4v . exceeding this common mode range will cause the open loop gain to drop significantly. for a unity gain amplifier, the output roughly tracks the input well beyond lt 6020 / lt 6020 -1 60201fa
14 for more information www.linear.com/lt6020 figure 5. increased ib beyond vicm 70 60 50 40 30 20 10 0 ?10 ?20 ?30 0 5 ?5?10?15 10 15 input common mode voltage (v) input bias current (a) 60201 f05 introduce errors comparable to or greater than the offset of the amplifiers. temperature differentials across the input connections can generate thermocouple voltages of tens of microvolts so the connections of the input leads should be short, close together and away from heat dis - sipating components . air currents across the board can also generate temperature differentials. as is the case with all amplifiers, a change in load current changes the finite open loop gain. increased load current reduces the open loop gain as seen in the typical performance characteristics section. this results in a change in input offset voltage. under large signal conditions with load currents of 2 ma the effective change in input error is just tens of microvolts. in precision applications it is important to consider amplifier loading when selecting feedback resistor values as well as the loads on the device. feedback components care must be taken to ensure that the pole formed by the feedback resistors and the parasitic capacitance at the inverting input does not degrade stability. for example, in a gain of +2 configuration, with 100 k feedback resistors and a poorly designed circuit board layout with parasitic capacitance of 10pf (amplifier + pc board) at the ampli - fiers inverting input will cause the amplifier to have poor phase margin due to a pole formed at 320 khz. an additional capacitor of 10 pf across the feedback resistor as shown in figure 6 will eliminate any ringing or oscillation. a pplica t ions i n f or m a t ion capacitive loads the lt6020 can drive capacitive loads up to 100 pf in unity gain. the capacitive load driving capability increases as the amplifier is used in higher gain configurations. a small series resistance between the output and the load will further increase the amount of capacitance that the amplifier can drive. shutdown operation (lt6020-1) the lt6020-1 shutdown function has been designed to be easily controlled from single supply logic or microcontollers. to enable the lt6020-1 when v dgnd = 0v the enable pin must be driven above 1.7 v. conversely, to enter the low power shutdown mode the enable pin must be driven below 0.8 v. in a 15 v dual supply application where v dgnd = C15 v, the enable pin must be driven above ~ C13.3 v to enable the lt6020-1. if the enable pin is driven below C14.2 v the lt6020-1 enters the low power shutdown mode. note that to enable the lt6020-1 the enable pin voltage can range from C13.3 v to 15 v whereas to disable the lt6020-1 the enable pin can range from C15v to C14.2 v. figure 7 shows examples of enable pin control. while in shutdown, the outputs of the lt6020-1 are high impedance. the lt6020-1 is typically capable of coming out of shutdown within 100 s. this is useful in power sensitive applications where duty cycled operation is employed such as wireless mesh networks. in these applications the system is in low power mode the majority of the time, but then needs to wake up quickly and settle for an acquisition before being powered back down to save power. figure 6. stability with parasitic input capacitance 100k 100k 10pf c par v out v in 60201 f06 + ? lt6020 lt 6020 / lt 6020 -1 60201fa
15 for more information www.linear.com/lt6020 a pplica t ions i n f or m a t ion figure 7. lt 6020 -1 enable pin control examples ?15 +15 off on ?14.2v ?13.3v dgnd high voltage split supplies to v + or en logic en 60201 f07 + ? lt6020-1 ?15 +15 off on 0.8v 1.7v dgnd high voltage split supplies to v + or en logic en + ? lt6020-1 +30 off on 0.8v 1.7v dgnd high voltage single supply to v + or en logic en + ? lt6020-1 +3v off on 0.8v 1.7v dgnd low voltage single supply to v + or en logic en + ? lt6020-1 ?1.5 +1.5 off on ?0.7v 0.2v dgnd low voltage split supplies to v + or en logic en + ? lt6020-1 typical a pplica t ions 60201 f02a v in v out ? + 1/2 lt6020 ? + 1/2 lt6020 270pf 10k 10k 4.7pf load 60201 f02b v in v out ? + 1/2 lt6020 ? + 1/2 lt6020 100 100 high open - loop gain composite amplifier parallel amplifiers achieves 32 nv / hz noise , doubles output drive and lowers offset lt 6020 / lt 6020 -1 60201fa
16 for more information www.linear.com/lt6020 p ackage descrip t ion please refer to http :// www . linear . com / designtools / packaging / for the most recent package drawings . 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (dd8) dfn 0509 rev c 0.25 0.05 2.38 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 0.05 (2 sides) 2.10 0.05 0.50 bsc 0.70 0.05 3.5 0.05 package outline 0.25 0.05 0.50 bsc dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698 rev c) lt 6020 / lt 6020 -1 60201fa
17 for more information www.linear.com/lt6020 p ackage descrip t ion please refer to http :// www . linear . com / designtools / packaging / for the most recent package drawings . 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) pin 1 notch r = 0.20 or 0.35 45 chamfer lt 6020 / lt 6020 -1 60201fa
18 for more information www.linear.com/lt6020 p ackage descrip t ion please refer to http :// www . linear . com / designtools / packaging / for the most recent package drawings . msop (ms8) 0213 rev g 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 ? 6 typ detail ?a? detail ?a? gauge plane 1 2 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev g) lt 6020 / lt 6020 -1 60201fa
19 for more information www.linear.com/lt6020 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 04/14 added ms8 package version. all lt 6020 / lt 6020 -1 60201fa
20 for more information www.linear.com/lt6020 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 2014 lt0414 rev a ? printed in usa (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt6020 r ela t e d p ar t s typical a pplica t ion part number description comments ltc6256 6.5mhz, 65a rrio op amp v os : 350v, gbw: 6.5mhz, sr: 1.8v/s, e n : 20nv/hz, i s : 65a lt1352 3mhz. 200v/s op amp v os : 600v, gbw: 3mhz, sr: 200v/s, e n : 14nv/hz, i s : 330a lt1492 5mhz, 3v/s op amp v os : 180v, gbw: 5mhz, sr: 3v/s, e n : 16.5nv/hz, i s : 550a ltc5800 smartmesh ? wireless sensor network i c wireless mesh networks LT5400 quad matched resistor network 0.01% matching 13.6 v input range mux buffer mux buffer response , 12 v step improved load drive capability gain of 11 instrumentation amplifier 60201 f03b v + v out v ? v in ? + lt6020 load 1k 2n3904 2n3906 60201 ta03c 1/2 ltc203 ?15v 15v in1 in2 s1 s2 gnd v + d1 d2 v ? 15v 15v v in1 ?6v v in2 6v ? + 1/2 lt6020 5 0 60201 f03a v inm r1 to r4: for high dc cmrr use LT5400-3 v inp ? + 1/2 lt6020 ? + 1/2 lt6020 r1, 100k ?3db bw = 30khz r2, 10k v out r3, 10k r4, 100k lt 6020 / lt 6020 -1 60201fa

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